1. Field of the Invention
The present Invention relates in general to a pattern generation device for semiconductor testing apparatus, and relates in particular to a test pattern generator device for generating high capacity patterns quickly.
2. Description of the Related Art
FIG. 3 shows a device configuration of a test pattern generator device for semiconductor testing apparatus according to the conventional technology. The device comprises: an address generator 21A; modifier register 22A; an adder 23A; a control circuit 24A; and an execution memory 25A having m-bit address space (where m is an integer).
When a test pattern is a small capacity pattern which can be accessed with an m-bit length address, the execution memory 25A is capable of storing several length of patterns, as in an example shown in FIG. 4. The data for the patterns are transferred from a magnetic disc device or other similar data storage device (not shown) to the execution memory 25A.
The test pattern generation operation of the conventional device shown in FIG. 3 will be explained in the following. First, under the action of the control circuit 24A, the leading address Ca0 of a pattern C (refer to FIG. 4) is stored in the modifier register 22A. Similarly, under the action of the control circuit 24A, the address generator 21A outputs successive addresses 0.sup..about. (2.sup.m -1). The m-bit address outputted by the address generator 21A and the m-bit data of the modifier register 22A are added by the adder 23A, and the resulting added addresses are outputted to the execution memory 25A. When the process is completed, the execution memory 25A outputs the test pattern C.
Similarly, when a test pattern D is to be outputted, the leading address Da0 is stored in the modifier register 22A, and when a test pattern E is to be outputted, the leading address Ea0 is stored in the modifier register 22A. Subsequently, following the similar steps as outlined above, pattern D or pattern E is outputted from the execution memory 25A.
With increasing-length of the test patterns, a need has arisen for enlarging the memory capacity in the semiconductor testing apparatus. However, fast and high capacity memories are very expensive, and enlarging the memory capacity of the execution memory device 25A, such as the one shown in FIG. 3, would result in a significant cost increase for the testing apparatus. For this reason, this problem has conventionally been dealt with by installing a high capacity but slow-speed buffer memory 25B such as the one shown in FIG. 5. The device configuration of this buffer memory will be explained in the following.
The pattern generator shown in FIG. 5 has additional components added to the test pattern generator shown in FIG. 3, i.e., a buffer memory 25B; address pointers 26A, 26B; and a selector 27A. The buffer memory 25B, the address pointers 26A, 26B and the selector 27A all generate output data of an n-bit length (where n is an integer and n&gt;m). The buffer memory 25B stores those patterns which are accessible with an address having less than n-bits.
FIG. 6 shows an example of a memory map for the buffer memory 25B, for the patterns A, B which are transferred by and stored in a magnetic disc (not shown). In this case, although the buffer memory 25B has an n-bit capability, the execution memory 25A has a shorter m-bit capability, and therefore, it is necessary that the patterns A, B be divided into groups of a size of less than m-bits that can be stored in the execution memory 25A. The pattern A is divided into groups of A-1, A-2 and A-3; and the pattern B is divided into groups of B-1, B-2, for example. The leading address data of these groups are stored as index I in other areas of the buffer memory 25B.
The operation of the buffer memory 25B is controlled by the control circuit 24A as follows. The control circuit commands so that address A1i which stores the leading address data of the pattern A-1 is inputted into the address pointer 26A. The control circuit 24A then issues a transfer command so that the selector 27A is switched to select the output of the address pointer 26A, and the leading address data of the pattern A-1 is read out from the buffer memory 25B and is stored in the address pointer 26B. Next, the selector 27A is switched to the output of the address pointer 26B. In this way, the pattern A-1 is successively forwarded to the execution memory 25A.
At this time, because the pattern A-1 is stored starting from the address location 2.sup.0 (=0) in the execution memory 25A. a [0] is stored in the modifier register 22. When the A-1 transfer process is completed, the leading address data A2i of the next pattern A-2 is stored in the address pointer 26A.
Next, the control circuit 24A commands the address generator 21A to generate successive addresses 0.sup..about. (2.sup.m -1). These m-bit addresses are supplied to the address in the execution memory 25A through the adder 23A so as to output the pattern A-1. This transfer command process is repeated to output the successive patterns A-2, A-3.
As summarized above, to generate large capacity patterns using the conventional pattern generator having a buffer memory and an execution memory, it is necessary to repeatedly perform tile pattern transfer process. This process is time-consuming and results in a lengthy testing time. It is also necessary to be aware of the capacity of the execution memory 25A in dividing the patterns into groups of suitable size as well as where to insert the transfer command so that the pattern generation process can be performed smoothly.
In recent years, there have been significant improvements achieved in mass production of high capacity semiconductor memories, and have resulted in lowering of the cost of fast high capacity memories. Therefore, there appear to be no obstacles to increasing the capacity of the execution memory, and it should be possible to generate high capacity patterns with a fast pattern generator device having a large capacity execution memory instead of a buffer memory.